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DATA SHEET
74LVC2G240 Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
Product specification 2003 Mar 11
Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
FEATURES * Wide supply voltage range from 1.65 to 5.5 V * 5 V tolerant input/output for interfacing with 5 V logic * High noise immunity * Complies with JEDEC standard: - JESD8-7 (1.65 to 1.95 V) - JESD8-5 (2.3 to 2.7 V) - JESD8B/JESD36 (2.7 to 3.6 V). * 24 mA output drive (VCC = 3.0 V) * CMOS low power consumption * Latch-up performance exceeds 250 mA * Direct interface with TTL levels * Inputs accept voltages up to 5 V * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. * Specified from -40 to +85 C and -40 to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD input capacitance power dissipation capacitance per buffer output enabled; notes 1 and 2 output disabled; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total switching outputs; (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC. DESCRIPTION
74LVC2G240
The 74LVC2G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pins nOE causes outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times.
TYPICAL 4.1 2.6 3.0 2.5 2.0 2 18 5 ns ns ns ns ns
UNIT
propagation delay inputs nA to output nY VCC = 1.8 V; CL = 30 pF; RL = 1 k
pF pF pF
2003 Mar 11
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
FUNCTION TABLE See note 1. INPUT nOE L L H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC2G240DP 74LVC2G240DC PINNING PIN 1 2 3 4 5 6 7 8 1OE 1A 2Y GND 2A 1Y 2OE VCC SYMBOL data input data output ground (0 V) data input data output output enable input (active LOW) supply voltage DESCRIPTION output enable input (active LOW) TEMPERATURE RANGE PINS -40 to +125 C -40 to +125 C 8 8 PACKAGE MATERIAL TSSOP8 VSSOP8 plastic plastic nA L H X
74LVC2G240
OUTPUT nY H L Z
CODE SOT505-2 SOT765-1
MARKING V240 V40
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
74LVC2G240
handbook, halfpage
handbook, halfpage
1OE 1 1A 2
8 VCC 7 2OE 1Y 2A
1 2 7 5
1OE 1A 2OE 2A 2Y 3 1Y 6
240
2Y GND 3 4
MNA957
6 5
MNA958
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1
EN
2
6
7
EN
5
MNA959
3
Fig.3 Logic symbol (IEEE/IEC).
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO PARAMETER supply voltage input voltage output voltage CONDITIONS 0 VCC = 1.65 to 5.5 V; enable mode 0 VCC = 1.65 to 5.5 V; disable mode 0 VCC = 0 V; Power-down mode Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 5.5 V 0 -40 0 0 MIN. 1.65
74LVC2G240
MAX. 5.5 5.5 VCC 5.5 5.5 +125 20 10 V V V V V
UNIT
C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO PARAMETER supply voltage input diode current input voltage output diode current output voltage VI < 0 note 1 VO > VCC or VO < 0 enable mode; notes 1 and 2 disable mode; notes 1 and 2 IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 3. Above 110 C the value of PD derates linearly with 8 mW/K. output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 to +125 C; note 3 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 50 +6.5 +6.5 50 100 +150 300 V mA V mA V V mA mA C mW UNIT
VCC + 0.5 V
Power-down mode; notes 1 and 2 -0.5
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO = - 24 mA IO = -32 mA ILI IOZ Ioff ICC ICC input leakage current 3-state output OFF-state current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 3.6 0 5.5 2.3 to 5.5 VCC - 0.1 1.2 1.9 2.2 2.3 3.8 - - - - - - - - - - - 0.1 0.1 0.1 0.1 5 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 - - - - - - - - - - - - 0.65 x VCC 1.7 2.0 0.7 x VCC - - - - - - - - - - - - VCC (V) MIN. TYP.(1)
74LVC2G240
MAX.
UNIT
- - - - 0.35 x VCC 0.7 0.8 0.3 x VCC 0.1 0.45 0.3 0.4 0.55 0.55 - - - - - - 5 10 10 10 500
V V V V V V V V V V V V V V V V V V V V A A A A A
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH HIGH-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VIL LOW-level input voltage 1.65 to 1.95 2.3 to 2.7 2.7 to 3.6 4.5 to 5.5 VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 4 mA IO = 8 mA IO = 12 mA IO = 24 mA IO = 32 mA VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -4 mA IO = -8 mA IO = -12 mA IO =- 24 mA IO = -32 mA ILI IOZ Ioff ICC ICC Note 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 C. input leakage current 3-state output OFF-state current power OFF leakage current quiescent supply current additional quiescent supply current per pin VI = 5.5 V or GND VI = VIH or VIL; VO = 5.5 V or GND VI or VO = 5.5 V VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 5.5 3.6 0 5.5 2.3 to 5.5 VCC - 0.1 0.95 1.7 1.9 2.0 3.4 - - - - - - - - - - - - - - - - 1.65 to 5.5 1.65 2.3 2.7 3.0 4.5 - - - - - - - - - - - - 0.65 x VCC 1.7 2.0 0.7 x VCC - - - - - - - - - - - - VCC (V) MIN.
74LVC2G240
TYP.(1)
MAX.
UNIT
- - - - 0.35 x VCC 0.7 0.8 0.3 x VCC 0.1 0.70 0.45 0.60 0.80 0.80 - - - - - - 20 20 20 40 5000
V V V V V V V V V V V V V V V V V V V V A A A A A
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
AC CHARACTERISTICS GND = 0 V. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C; note 1 tPHL/tPLH propagation delay nA to nY see Figs 4 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPZH/tPZL 3-state output enable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Tamb = -40 to +125 C tPHL/tPLH propagation delay nA to nY see Figs 4 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPZH/tPZL 3-state output enable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 tPHZ/tPLZ 3-state output disable time nOE to nY see Figs 5 and 6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 4.5 to 5.5 Note 1. All typical values are measured at Tamb = 25 C. 1.0 0.5 1.0 0.5 0.5 1.5 1.0 1.5 0.5 0.5 1.0 0.5 1.0 1.0 0.5 - - - - - - - - - - - - - - - 1.0 0.5 1.0 0.5 0.5 1.5 1.0 1.5 0.5 0.5 1.0 0.5 1.0 1.0 0.5 4.1 2.6 3.0 2.5 2.0 4.5 2.9 3.4 2.5 2.0 3.5 1.9 2.8 2.7 1.9 VCC (V) MIN. TYP.
74LVC2G240
MAX.
UNIT
9.5 5.2 5.5 4.6 4.0 10.3 5.6 5.6 4.7 3.8 11.6 5.8 4.5 4.4 3.4
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
11.9 6.5 6.9 5.8 5.0 12.9 7.0 7.0 5.9 4.8 14.1 7.6 5.8 5.7 4.6
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
AC WAVEFORMS
74LVC2G240
V handbook, halfpage I nA input GND t PHL VOH nY output VOL VM VM
MNA960
VM
VM
t PLH
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V 4.5 to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 The input (nA) to output (nY) propagation delays and the output transition times.
2003 Mar 11
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
74LVC2G240
handbook, full pagewidth
VI nOE input GND t PLZ VCC output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
MNA961
VM
t PZL
VM VX t PZH VY VM
INPUT VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V 4.5 to 5.5 V VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC VCC VCC 2.7 V 2.7 V VCC VI tr = tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns
VX = VOL + 0.3 V at VCC 2.7 V; VX = VOL + 0.15 V at VCC < 2.7 V; VY = VOH - 0.3 V at VCC 2.7 V; VY = VOH - 0.15 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5 3-state enable and disable times for input nOE.
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
74LVC2G240
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V 4.5 to 5.5 V
VI VCC VCC 2.7 V 2.7 V VCC
CL 30 pF 30 pF 50 pF 50 pF 50 pF
RL 1 k 500 500 500 500
VEXT tPLH/tPHL open open open open open tPZH/tPHZ GND GND GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 6V 6V 2 x VCC
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
PACKAGE OUTLINES
74LVC2G240
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
74LVC2G240
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferably be kept: * below 220 C for all the BGA packages and packages with a thickness 2.5 mm and packages with a thickness <2.5 mm and a volume 350 mm3 so called thick/large packages * below 235 C for packages with a thickness <2.5 mm and a volume <350 mm3 so called small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
74LVC2G240
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes not suitable not suitable(3)
74LVC2G240
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74LVC2G240
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
NOTES
74LVC2G240
2003 Mar 11
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
NOTES
74LVC2G240
2003 Mar 11
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Philips Semiconductors
Product specification
Dual buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
NOTES
74LVC2G240
2003 Mar 11
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp20
Date of release: 2003
Mar 11
Document order number:
9397 750 11082

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